Document Type
Report
Date
7-1989
Keywords
Combinational circuits
Language
English
Disciplines
Computer Sciences
Description/Abstract
In this report we present a new algorithm for detecting single stuck-at faults in combinational circuits. This algorithm is based on a 15-valued system and introduces several new concepts to make test generation more efficient. This 15-valued system allows us to impose all the constraints that must be satisfied in order to sensitize a single path. Consequently all deterministic implications are fully considered prior to the enumeration process. The resulting ability to identify inconsistencies prior to enumeration improves the possibility of quicker identification of redundant faults. Instead of sensitizing a single gate at a time, we sensitize subpaths by sensitizing all gates lying between successive fanout stems and then consider the deterministic implications of such a sensitization. We have introduced several speed-up techniques that effectively combine the information provided by the deterministic path sensitization and that obtained from the circuit topology. These techniques improve the efficiency of the enumeration phase by substantially pruning the search space.
Recommended Citation
Uz Zaman, Akhtar; Ali, M.; and Hartmann, Carlos R.P., "A 15-Valued Algorithm for Test Pattern Generation" (1989). Electrical Engineering and Computer Science - Technical Reports. 54.
https://surface.syr.edu/eecs_techreports/54
Source
local
Additional Information
School of Computer and Information Science, Syracuse University, SU-CIS-89-02