Document Type
Report
Date
6-1991
Keywords
combinational circuits
Language
English
Disciplines
Computer Sciences
Description/Abstract
A 16-valued logic system for testing combinational circuits is presented. This logic system has been used to develop SIMPLE, an efficient test generation algorithm for single stuck-at faults. The proposed scheme for testing stuck-at faults is based on imposing all the constraints that must be satisfied in order to sensitize a path from a fault site to a primary output. Consequently all deterministic implications are fully considered prior to the enumeration process. The resulting ability to identify inconsistencies prior to enumeration improves the possibility of quicker identification of redundant faults. In order to prune the search space we have introduced several speed-up techniques that effectively combine the information provided by the deterministic path sensitization and that obtained from the circuit topology. Some properties of undetectable faults are presented and methods to identify them without actual test generation are proposed.
Recommended Citation
Uz Zaman, Akhtar; Ali, M.; and Hartmann, Carlos R.P., "A Sixteen-Valued Algorithm for Test Generation in Combinational Circuits" (1991). Electrical Engineering and Computer Science - Technical Reports. 114.
https://surface.syr.edu/eecs_techreports/114
Source
local
Additional Information
School of Computer and Information Science, Syracuse University, SU-CIS-91-18