Document Type
Article
Date
1998
Keywords
space-time adaptive processing algorithms, STAP
Language
English
Disciplines
Computer Sciences
Description/Abstract
Performance results are presented for the design and implementation of parallel pipelined space-time adaptive processing (STAP) algorithms on parallel computers. In particular, the issues involved in parallelization, our approach to parallelization, and performance results on an Intel Paragon are described. The process of developing software for such an application on parallel computers when latency and throughput are both considered together is discussed and tradeoffs considered with respect to inter and intratask communication and data redistribution are presented. The results show that not only scalable performance was achieved for individual component tasks of STAP but linear speedups were obtained for the integrated task performance, both for latency as well as throughput. Results are presented for up to 236 compute nodes (limited by the machine size available to us). Another interesting observation made from the implementation results is that performance improvement due to the assignment of additional processors to one task can improve the performance of other tasks without any increase in the number of processors assigned to them. Normally, this cannot be predicted by theoretical analysis.
Recommended Citation
Choudhary, Alok; Liao, Wei-keng; Weiner, Donald; Varshney, Pramod; Linderman, Richard; and Linderman, Mark, "Design, implementation, and evaluation of parallell pipelined STAP on parallel computers" (1998). Electrical Engineering and Computer Science - All Scholarship. 49.
https://surface.syr.edu/eecs/49
Additional Information
First and Syracuse University authors listed; for a complete list of authors, please refer to the article.