Date of Award


Degree Type


Degree Name

Master of Science (MS)


Electrical Engineering and Computer Science


Ghosh, Prasanta

Subject Categories

Electrical and Computer Engineering | Engineering


An Operational Transconductance Amplifier (further abbreviated as OTA) is a voltage controlled current source used to produce an output current proportional to the input voltage. A schematic architecture for a 180nm OTA is presented in this thesis with the goal of improving the open-loop gain for a 0.9V supply voltage with a rail-to-rail bulk-driven input stage. Results show an open loop gain 97.14 dB with a power consumption of 3.33uW. An OTA with over 90 dB open loop gain and lower power consumption is highly suitable for low-voltage applications. The slew rate of the OTA is 0.05V/uS with a unity-gain bandwidth of 8.4MHz. A 10uA ideal bias current reference is utilized for the design. The phase margin is around 49.2 degrees.

The threshold voltage for a 180nm N-channel Metal Oxide Semiconductor (also known as NMOS) device is around 400mV which restricts the low voltage applications in most amplifier circuits. The fourth terminal (bulk) of the MOS device is utilized to optimize the voltage headroom (Vds). The bulk terminal uses a much lesser source to drain voltage than the gate-driven transistors, and the transistors remain ON with an input voltage as low as 0.1V. A bulk-driven input stage ensures the amplification in the subthreshold region (input signal less than the threshold voltage of the MOS device). However, even with the bulk input MOS device, a rail-to-rail input stage is employed to improve the dynamic range for the input signal from 0V to 0.9V with a supply voltage of 0.9V. The fluctuation in open loop gain concerning the change in input signal in the published research is because of the constant instability in the intrinsic transconductance of the input devices. A possible solution is presented in this thesis by adding a second dominant pole to the circuit (i.e., second stage for the OTA), which reduces the dependency of intrinsic transconductance (bulk-driven device) on the total open loop gain of the amplifier. Thus, a significant gain of 97.14 dB with minimal fluctuations is achieved. Furthermore, adding a second stage improves the gain by distributing the dependency of the gain due to the first stage to both poles in the circuit. Hence, the problem of fluctuating transconductance of the input stage is resolved by the constant intrinsic transconductance of the MOS near the second pole (M19).

To improve the gain, a folded cascoded amplifier connected with the input stage results in a better impedance (in the first stage) known as the gain stage. In the second stage, a large PMOS common source amplifier gives a good output current compared to the input stage to enhance the output swing and drive a purely capacitive load of 0.5pF. Furthermore, a miller capacitance is used to compensate for the frequency between the first and the second stage and improving the unity-gain bandwidth. An additional biasing circuit in the second stage amplifies the current output of the first stage and thus improving the slew rate of the entire device. In addition, the biasing circuit resolves the biasing issues for the second-stage common-source amplifier. It improves the output swing of the device to obtain a clean/undistorted output waveform. All the simulations are carried out in the LTSpice simulation tool to test the waveforms and bode plot for open loop gain and phase margin (49.2 degrees) at different processes (slow, typical, and fast), input voltages (0-0.9V), supply voltage (0.8V, 0.9V, 1.0V) and temperatures (-10 to 100 degree C).


Open Access



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