Dual-Mode Combinational Logic for Function-Independent Fault Testing

Sumit DasGupta, Syracuse University
Carlos R.P. Hartmann, Syracuse University
Luther D. Rudolph, Syracuse University



This paper presents a method of using hardware redundancy to ease the problem of fault testing in combinational logic networks. Combinational logic networks are constructed using dual-mode logic gates. Initially, it is shown that these networks can be tested for all single stuck-at-faults using just two function-independent tests. This method is then extended to detect a large class of multiple faults with the same two function-independent tests.