Document Type

Report

Date

2-1977

Embargo Period

4-25-2012

Keywords

Logic

Language

English

Disciplines

Computer Sciences

Description/Abstract

This paper presents a method of using hardware redundancy to ease the problem of fault testing in combinational logic networks. Combinational logic networks are constructed using dual-mode logic gates. Initially, it is shown that these networks can be tested for all single stuck-at-faults using just two function-independent tests. This method is then extended to detect a large class of multiple faults with the same two function-independent tests.

Source

local

Share

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