Document Type

Report

Date

6-1991

Embargo Period

5-2-2012

Keywords

combinational circuits

Language

English

Disciplines

Computer Sciences

Description/Abstract

A 16-valued logic system for testing combinational circuits is presented. This logic system has been used to develop SIMPLE, an efficient test generation algorithm for single stuck-at faults. The proposed scheme for testing stuck-at faults is based on imposing all the constraints that must be satisfied in order to sensitize a path from a fault site to a primary output. Consequently all deterministic implications are fully considered prior to the enumeration process. The resulting ability to identify inconsistencies prior to enumeration improves the possibility of quicker identification of redundant faults. In order to prune the search space we have introduced several speed-up techniques that effectively combine the information provided by the deterministic path sensitization and that obtained from the circuit topology. Some properties of undetectable faults are presented and methods to identify them without actual test generation are proposed.

Additional Information

School of Computer and Information Science, Syracuse University, SU-CIS-91-18

Source

local

Share

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