compiler algorithm, algorithms, cache locality, nests
This paper describes an algorithm to optimize cache locality in scientific codes on uniprocessor and multiprocessor machines. A distinctive characteristic of our algorithm is that it considers loop and data layout transformations in a unified framework. We illustrate through examples that our approach is very effective at reducing cache misses and tile size sensitivity of blocked loop nests; and can optimize nests for which optimization techniques based on loop transformations alone are not successful. An important special case is the one in which data layouts of some arrays are fixed and cannot be changed. We show how our algorithm can handle this case, and demonstrate how it can be used to optimize multiple loop nests.
Kandemir, Mahmut; Ramanujam, J.; and Choudhary, Alok, "A Compiler Algorithm for Optimizing Locality in Loop Nests" (1997). Electrical Engineering and Computer Science. Paper 31.