Document Type

Report

Date

11-23-2010

Embargo Period

3-30-2011

Keywords

Bit Serial, Floating Point, FPGA, Parallelism, State Space Formulation

Language

English

Disciplines

Electrical and Computer Engineering

Description/Abstract

In this paper we discuss the pros and cons of bit serial arithmetic for performing mathematical operations for signal processing and scientific computations on an FPGA. We describe our formulation of the architecture for such massively parallel systems, the advantage being that it requires no parallel programming in the traditional sense. We describe a pseudo floating point bit serial circuit which is less complex than full precision floating point and show that it is suitable for many applications. We conclude with several application examples and show that a bit serial implementation can be competitive with a high speed parallel implementation.

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local input

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