Document Type
Article
Date
1995
Embargo Period
1-2012
Keywords
Field-Programmable Gate Arrays, FPGAs, FPGA faults, Simulation
Language
English
Disciplines
Computer Sciences
Description/Abstract
Although Field-Programmable Gate Arrays (FPGAs) are tested by their manufacturers prior to shipment, they are still susceptible to failures in the field. In this paper, test vectors generated for the emulated (i.e., mission) circuit are fault simulated on two different models: the original view of the circuit, and the design as it is mapped to the FPGA's logic cells. Faults in the cells and in the programming logic are considered. Experiments show that this commonly-used approach fails to detect most of the faults in the FPGA.
Recommended Citation
Kwiat, Kevin A.; Debany, Warren; and Hariri, Salim, "Effects of Technology Mapping on Fault Detection Coverage in Reprogrammable FPGAs" (1995). Electrical Engineering and Computer Science. Paper 165.
http://surface.syr.edu/eecs/165